1. Field of the Invention
This invention relates generally to differential voltage comparator circuits. In particular, the invention provides a differential voltage comparator having matched input characteristics and substantially symmetrical response to variations on either input, while providing increased speed and sensitivity.
2. Description of the Prior Art
Differential comparators typically comprise a first stage differential amplifier having a current mirrored active load with an output driving a second stage output structure. Differential comparators may be constructed using either bipolar or metal oxide semiconductors (MOS) elements. An example of the prior art using MOS technology is shown in FIG. 1.
The combination of relatively high transconductance at low current and linearity of transconductance with current for bipolar devices makes bipolar technology superior for most high speed applications of differential comparators similar to the prior art shown. However, the use of MOS devices provides simplicity in design and processing particularly where a comparator circuit is required on chip in large scale integrated circuits using MOS technology. Use of a MOS differential comparator avoids the requirement for mixing bipolar technology processing with MOS processing.
In the prior art as seen in FIG. 1, the loading condition on the two inputs, V.sub.X and V.sub.Y, is typically different due to Miller feedback capacitance of the normally connected leg of the differential structure as opposed to the diode connected leg. This difference in loading conditions may significantly affect response of the circuit to inputs having matched output impedance or may adversely affect the circuit structures providing the input. Further, because of the difference in the differential structure, switching speed of the output is dependant upon which of the input values V.sub.X or V.sub.Y varies. Switching of the differential output to a high condition may be substantially longer than switching low. When input V.sub.X is less than input V.sub.Y, current through the diode connected transistor in the active load becomes greater thereby charging the common gate node of the current mirror. This node has gate to source capacitance of both transistors of the current mirror. As the common gate node charges, the mirrored transistor sinks current from the differential output until a steady state is reached. Conversely, when V.sub.Y decreases below V.sub.X , additional current is sourced directly to the differential output. The higher capacitance of the common gate node of the current mirror therefore delays the transfer of steady state differential output current when sinking current as opposed to sourcing current.
In a MOS application in the prior art, overall speed of the differential comparator may be recovered to some extent by reducing gate length of the input MOS devices to increase their transconductance. As gate length is decreased, however, voltage gain, which is limited by the drain impedance of the MOS devices, decreases. This reduction in gain is undesirable for the comparator since overall accuracy of the device is reduced. Similarly, if width of the MOS input devices is increased to provide increased transconductance greater parasitic node capacitance will exist at the output of the differential stage. The improvement in delay time across the device therefore decreases with increasing device width, but approaches an asymptotic limit. In addition, increased device width increases the overall input capacitance of the comparator resulting in an increase in overall delay of the circuit when devices providing V.sub.X and V.sub.Y inputs to the comparator have significant output impedance thereby increasing the time to charge the input capacitance of the circuit.
Prior art comparator circuits embodied in MOS devices encounter an additional problem when input voltages to be compared become large. This condition requires the power supply voltage for the differential comparator to be increased to permit proper operation at higher operation voltages. When V.sub.X is significantly greater than V.sub.Y, impact ionization may occur at the drain of the normally connected MOS device in the current mirror load. If impact ionization occurs, the MOS transistor may degrade over time. Such degradation results in excess input offset voltages, a loss of voltage gain and increased delay in the circuit.